Hardware Reference
In-Depth Information
statement associated with the outputs because in a Moore machine the outputs depend
solely on the state in which the machine is, so for a given state each output value/
expression is unique.
7) The third and i nal
always
block (lines 50-58) implements the optional output
register (always 3 block of i gure 7.2). Note that it simply copies each original output
to a new output at every positive clock edge (it could also be at the negative edge),
thus inferring the extra register. If this register is used, then the names of the new
outputs must obviously be the names used in the corresponding port declarations (line
9). If the initial output values do not matter, reset is not required in this register.
8) To conclude, observe the completeness of the code and the correct use of registers
(as requested in sections 4.2.8 and 4.2.9, respectively), summarized below.
a) Regarding the use of registers: The circuit is not overregistered. This can be
observed in the
always_ff
statement of line 20 (responsible for the inference of
l ip-l ops), which is closed in line 22, guaranteeing that only the machine state
(line 22) gets registered. The output is in the
always_comb
block, which is purely
combinational.
b) Regarding the outputs: The list of outputs (
outp1
,
outp2
, …) is exactly the same
in all states (see lines 28-30, 36-38, . . .), and the output values/expressions are
always declared.
c) Regarding the next state: Again, the coverage is complete because all states (A,
B, C, . . .) are included and in each state the conditional declarations are i nalized
with an
else
statement (lines 33, 41, . . .), guaranteeing that no condition is left
unchecked.
Note:
Another implementation approach, for simple FSMs, will be seen in chapter 15.
1 //Part 1: Module header:-----------------------------
2 module module_name
3
#(parameter
4
param1 = <value>,
5
param2 = <value>)
6
(
7
input logic clk, rst, ...
8
input logic [7:0] inp1, inp2, ...
9
output logic [15:0] outp1, outp2, ...);
10
11 //Part 2: Declarations:------------------------------
12
13
//FSM states type:
14
typedef enum logic [2:0] {A, B, C, ...} state;
15
state pr_state, nx_state;
16
17 //Part 3: Statements:--------------------------------
18
19
//FSM state register:
20
always_ff @(posedge clk, posedge rst)
21
if (rst) pr_state <= A;
22
else pr_state <= nx_state;
23
