Hardware Reference
In-Depth Information
24
//FSM combinational logic:
25
always_comb
26
case (pr_state)
27
A: begin
28
outp1 <= <value>;
29
outp2 <= <value>;
30
...
31
if (condition) nx_state <= B;
32
else if (condition) nx_state <= ...;
33
else nx_state <= A;
34
end
35
B: begin
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outp1 <= <value>;
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outp2 <= <value>;
38
...
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if (condition) nx_state <= C;
40
else if (condition) nx_state <= ...;
41
else nx_state <= B;
42
end
43
C: begin
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...
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end
46
...
47
endcase
48
49
//Optional output register:
50
always_ff @(posedge clk, posedge rst)
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if (rst) begin //rst might be not needed here
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new_outp1 <= ...;
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new_outp2 <= ...; ...
54
end
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else begin
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new_outp1 <= outp1;
57
new_outp2 <= outp2; ...
58
end
59
60 endmodule
61 //---------------------------------------------------
7.4 SystemVerilog Template for Regular (Category 1) Mealy Machines
This template, also based on i gures 7.1 and 7.2, is presented below. The only differ-
ence with respect to the Moore template just presented is in the
always_comb
block
for the combinational logic because the output is specii ed differently now. Recall that
in a Mealy machine the output depends not only on the FSM's state but also on its
input, so
if
statements are expected for the output in one or more states because the
output values might not be unique. This is achieved by including the output
within
the conditional statements for
nx_state
. For example, observe in lines 15-33, relative
to state A, that the output values are now conditional. Compare these lines against
lines 27-34 in the previous template.
Please read all comments made for the Moore template in section 7.3 because,
except for the difference mentioned above, they all apply to the Mealy template below
