Hardware Reference
In-Depth Information
Figure 7.2
State machine architecture depicting how the SystemVerilog code was broken (three
always
blocks).
3) for the optional output register. Note the asterisk on one of the input connections;
as we know, if that connection exists it is a Mealy machine, else it is a Moore machine.
There obviously are other ways of breaking the code instead of using the three
always
blocks indicated in i gure 7.2. For example, the combinational logic section
could be implemented with two
always
blocks, one with the logic for
output
, the other
with the logic for
nx_state
.
The SystemVerilog template for the design of category 1 Moore machines is pre-
sented below. Observe the following:
1) To improve readability, the three fundamental code sections were separated by
dashed lines (lines 1, 11, 17, 61).
2) The i rst part of the code is the module header, in lines 1-9. It contains two sec-
tions: global parameter declarations (optional, lines 3-5) and circuit ports (mandatory
for synthesis, lines 7-9). Note that all ports are of type
logic
, with one or more bits.
3) The second part of the code is the declarations part, in lines 11-15. A special enu-
merated type, called
state
, is created in line 14, then the signals
pr_state
and
nx_state
are declared using that type in line 15.
4) The third part of the code is the statements part (code proper), in lines 17-60. In
this template, it contains three
always
blocks, described next.
5) The i rst
always
block (lines 20-22) is an
always_ff
because we want l ip-l ops to
be inferred. It implements the machine's state register (always 1 block of i gure 7.2).
This register is reset when
rst
='1' occurs; if
rst
='0', the input is copied to the output at
every positive clock edge.
6) The second
always
block (lines 25-47) is an
always_comb
because we want a
purely combinational circuit to be inferred (see always 2 block in i gure 7.2). This part
must contain all states (A, B, C, . . .), and for each state two things must be declared:
the output values/expressions and the next state. Note, for example, in lines 27-34,
relative to state A, the output declarations in lines 28-30 and the next state declara-
tions in lines 31-33. A very important point to observe here is that there is no
if
