Hardware Reference
In-Depth Information
7 SystemVerilog Design of Regular (Category 1) State Machines
7.1 Introduction
This chapter presents several SystemVerilog designs of category 1 state machines. It
starts by presenting two SystemVerilog templates, for Moore- and Mealy-based imple-
mentations, which are used subsequently to develop a series of designs related to the
examples introduced in chapter 5.
The codes are always complete (not only partial sketches) and are accompanied by
comments and simulation results illustrating the design's main features. All circuits
were synthesized using Quartus II (from Altera) or ISE (from Xilinx). The simulations
were performed with Quartus II or ModelSim (from Mentor Graphics). The default
encoding scheme for the states of the FSMs was regular sequential encoding (see
encoding options in section 3.7).
The same designs were developed in chapter 6 using VHDL, so the reader can make
a direct comparison between the codes.
Note:
See suggestions of SystemVerilog topics in the bibliography.
7.2 General Structure of SystemVerilog Code
A typical structure of SystemVerilog code for synthesis, with all elements that will be
needed in this and in coming chapters, is depicted in i gure 7.1. It is composed of
three fundamental sections, briel y described below.
Module Header
The
module
header is similar to
entity
in VHDL (section 6.2), also divided into two
parts, called
parameter declarations
and
port declarations
.
Parameter declarations:
This portion, similar to
generic
in VHDL, is optional. It
is used for the declaration of global parameters, which can be easily modii ed to
fuli ll different system specii cations or, more importantly, can be overridden during
instantiations into other designs (structural code).
