Hardware Reference
In-Depth Information
Figure 6.6
c) Physically test your design by connecting an actual keypad (or an arrangement of
pushbuttons) to the FPGA in your development board, with
key
displayed by one of
the board's SSDs.
Exercise 6.8: Datapath Controller for a Largest-Value Detector
This exercise concerns the control unit treated in exercise 5.15.
a) Solve exercise 5.15 if not done yet.
b) Implement the FSM obtained above using VHDL. Present meaningful simulation
results.
