Hardware Reference
In-Depth Information
30
begin
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case pr_state is
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when idle =>
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selA <= '-';
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selB <= '-';
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wrA <= '0';
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wrB <= '0';
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ALUop <= "00";
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if dv='1' then
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nx_state <= load;
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else
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nx_state <= idle;
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end if;
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when load =>
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selA <= '1';
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selB <= '1';
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wrA <= '1';
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wrB <= '1';
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ALUop <= "00";
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nx_state <= waitt;
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when waitt =>
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selA <= '-';
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selB <= '-';
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wrA <= '0';
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wrB <= '0';
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ALUop <= "10";
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if sign="01" then
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nx_state <= writeA;
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elsif sign="10" then
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nx_state <= writeB;
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else
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nx_state <= idle;
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end if;
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when writeA =>
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selA <= '0';
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selB <= '-';
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wrA <= '1';
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wrB <= '0';
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ALUop <= "10";
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nx_state <= waitt;
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when writeB =>
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selA <= '-';
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selB <= '0';
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wrA <= '0';
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wrB <= '1';
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ALUop <= "11";
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nx_state <= waitt;
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end case;
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end process;
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80 end architecture;
81 -----------------------------------------------------
Simulation results are presented in i gure 6.5. The encoding chosen for the states
was
sequential
(section 3.7). The states are enumerated from 0 to 4 (there are i ve states)
