Hardware Reference
In-Depth Information
Figure 6.5
Simulation results from the VHDL code for the control unit of i gure 5.13e, which controls a
datapath for GCD calculation.
in the order in which they were declared in line 14 (be aware, however, that some
compilers reserve the value zero for the reset state). The stimuli are exactly as in i gure
5.13d (GCD for 9 and 15). The reader is invited to inspect these results and compare
them against the waveforms in i gure 5.13d.
6.9 Exercises
Exercise 6.1: Parity Detector
This exercise concerns the parity detector of i gure 5.5c.
a) How many l ip-l ops are needed to implement it with sequential and one-hot
encoding?
b) Implement it using VHDL. Check whether the number of DFFs inferred by the
compiler matches each of your predictions.
c) Simulate it using the same stimuli of i gure 5.5b and check if the same waveform
results for
y
.
Exercise 6.2: One-Shot Circuits
This exercise concerns the one-shot circuits of i gures 5.7c,d.
a) Solve exercise 5.5 if not done yet.
b) How many l ip-l ops are needed to implement each FSM with sequential
encoding?
c) Implement both circuits using VHDL. Check whether the number of DFFs inferred
by the compiler matches each of your predictions.
d) Simulate each circuit using the same stimuli of exercise 5.5 (i gure 5.16) and check
whether the same results are obtained here.
