Hardware Reference
In-Depth Information
The second and i nal process (lines 29-78) implements the entire combinational
logic section. It is just a list of all states, each containing the output values and the
next state. Note that in each state the output values are unique because in a Moore
machine the outputs depend only on the state in which the machine is.
Observe the correct use of registers and the completeness of the code, as described
in comment 10 of section 6.3. Note in particular the following:
1) Regarding the use of registers: The circuit is not overregistered. This can be observed
in the
elsif rising_edge(clk)
statement of line 23 (responsible for the inference of
l ip-l ops), which is closed in line 25, guaranteeing that only the machine state (line
24) gets stored. The outputs are in the next process, which is purely combinational
(thus not registered).
2) Regarding the outputs: The list of outputs (
selA
,
selB
,
wrA
,
wrB
,
ALUop
) is exactly
the same in all states (see lines 33-37, 44-48, 51-55, . . .), and the corresponding
output values are always properly declared.
3) Regarding the next state: Again, the coverage is complete because all states are
included (see lines 32, 43, 50, . . .), and in each state any conditional declarations for
the next state are i nalized with an
else
statement (lines 40 and 60), guaranteeing that
no condition is left unchecked.
1 -----------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 -----------------------------------------------------
5 entity control_unit_for_GCD is
6 port (
7 dv, clk, rst: in std_logic;
8 sign: in std_logic_vector(1 downto 0)
9 selA, selB, wrA, wrB: out std_logic;
10 ALUop: out std_logic_vector(1 downto 0));
11 end entity;
12 -----------------------------------------------------
13 architecture moore_fsm of control_unit_for_GCD is
14 type state is (idle, load, waitt, writeA, writeB);
15 signal pr_state, nx_state: state;
16 begin
17
18
--FSM state register:
19
process (clk, rst)
20
begin
21
if rst='1' then
22
pr_state <= idle;
23
elsif rising_edge(clk) then
24
pr_state <= nx_state;
25
end if;
26
end process;
27
28
--FSM combinational logic:
29
process (all) --or (pr_state, dv, sign)
