Hardware Reference
In-Depth Information
Observe the correct use of registers and the completeness of the code, as described
in comment 10 of section 6.3. Note in particular the following:
1) Regarding the use of registers: The circuit is not overregistered. This can be observed
in the
elsif rising_edge(clk)
statement of line 21 (responsible for the inference of
l ip-l ops), which is closed in line 23, guaranteeing that only the machine state (line
22) gets stored. The output (
outp
) is in the next process, which is purely combinational
(thus not registered).
2) Regarding the outputs: The list of outputs (just
outp
in this example) is exactly the
same in all states (see lines 31, 42, 53, 64, 75), and the corresponding output values
are always properly declared.
3) Regarding the next state: Again, the coverage is complete because all states are
included (see lines 30, 41, 52, 63, 74), and in each state the conditional declarations
for the next state are always i nalized with an
else
statement (lines 38, 49, 60, 71, 82),
guaranteeing that no condition is left unchecked.
1 -------------------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 -------------------------------------------------------------
5 entity counter is
6 port (
7 ena, up, clk, rst: in std_logic;
8 outp: out std_logic_vector(2 downto 0));
9 end entity;
10 -------------------------------------------------------------
11 architecture moore_fsm of counter is
12 type state is (one, two, three, four, five);
13 signal pr_state, nx_state: state;
14 begin
15
16
--FSM state register:
17
process (clk, rst)
18
begin
19
if rst='1' then
20
pr_state <= one;
21
elsif rising_edge(clk) then
22
pr_state <= nx_state;
23
end if;
24
end process;
25
26
--FSM combinational logic:
27
process (all) --list proc. inputs if "all" not supported
28
begin
29
case pr_state is
30
when one =>
31
outp <= "001";
32
if ena='1' then
33
if up='1' then
34
nx_state <= two;
35
else
