Hardware Reference
In-Depth Information
36
nx_state <= five;
37
end if;
38
else
39
nx_state <= one;
40
end if;
41
when two =>
42
outp <= "010";
43
if ena='1' then
44
if up='1' then
45
nx_state <= three;
46
else
47
nx_state <= one;
48
end if;
49
else
50
nx_state <= two;
51
end if;
52
when three =>
53
outp <= "011";
54
if ena='1' then
55
if up='1' then
56
nx_state <= four;
57
else
58
nx_state <= two;
59
end if;
60
else
61
nx_state <= three;
62
end if;
63
when four =>
64
outp <= "100";
65
if ena='1' then
66
if up='1' then
67
nx_state <= five;
68
else
69
nx_state <= three;
70
end if;
71
else
72
nx_state <= four;
73
end if;
74
when five =>
75
outp <= "101";
76
if ena='1' then
77
if up='1' then
78
nx_state <= one;
79
else
80
nx_state <= four;
81
end if;
82
else
83
nx_state <= five;
84
end if;
85
end case;
86
end process;
87
88 end architecture;
89 -------------------------------------------------------------
Synthesis results using the VHDL code above are presented in i gure 6.3. The cir-
cuit's structure can be seen in the RTL view of
i gure 6.3a, while the FSM can be seen
