Hardware Reference
In-Depth Information
44
output1 <= <value>;
45
output2 <= <value>;
46
...
47
nx_state <= ...;
48
else
49
output1 <= <value>;
50
output2 <= <value>;
51
...
52
nx_state <= B;
53
end if;
54
when C =>
55
...
56
end case;
57
end process;
58
59
--Optional output register:
60
(same as for category 1 Moore, section 6.3)
61
62 end architecture;
63 -------------------------------------------------------------
6.6 Design of a Small Counter
This section presents a VHDL-based design for the 1-to-5 counter with enable and
up-down controls introduced in section 5.4.1 (i gure 5.3).
Because counters are inherently synchronous, the Moore approach is the natural
choice for their implementation, so the VHDL template of section 6.3 is used. Because
possible glitches during (positive) clock transitions are generally not a problem in
counters, the optional output register shown in the last process of the template is not
employed.
The entity, called
counter
, is in lines 5-9. All ports are of type
std_logic
or
std_logic_
vector
(industry standard).
The architecture, called
moore_fsm
, is in lines 11-88. As usual, it contains a declara-
tive part (before the keyword
begin
) and a statements part (from
begin
on).
In the declarative part of the architecture (lines 12-13), the enumerated type
state
is created to represent the machine's present and next states. Recall that when neither
the
enum_encoding
nor the
fsm_encoding
attribute is used, the encoding scheme must
be selected in the compiler's setup.
The i rst process (lines 17-24) in the statements part implements the state register.
As in the template, this is a standard code with clock and reset present only in this
process.
The second and i nal process (lines 27-86) implements the entire combinational
logic section. It is just a list of all states, each containing the output value and the
next state. Note that in each state the output value is unique because in a Moore
machine the output depends only on the state in which the machine is.
