Hardware Reference
In-Depth Information
36
when A =>
37
output1 <= <value>;
38
output2 <= <value>;
39
...
40
if <condition> then
41
nx_state <= B;
42
elsif <condition> then
43
nx_state <= ...;
44
else
45
nx_state <= A;
46
end if;
47
when B =>
48
output1 <= <value>;
49
output2 <= <value>;
50
...
51
if <condition> then
52
nx_state <= C;
53
elsif <condition> then
54
nx_state <= ...;
55
else
56
nx_state <= B;
57
end if;
58
when C =>
59
...
60
end case;
61
end process;
62
63
--Optional output register:
64
process (clk, rst)
65
begin
66
if rst='1' then --rst generally optional here
67
new_output1 <= ...;
68
...
69
elsif rising_edge(clk) then
70
new_output1 <= output1;
71
...
72
end if;
73
end process;
74
75 end architecture;
76 -------------------------------------------------------------
Final Comments
1) On the need for a reset signal: Note in the template above that the sequential
portion of the FSM (process of lines 23-30) has a reset signal. As seen in sections 3.8
and 3.9, that is the usual situation. However, as also seen in those sections, if the
circuit is implemented in an FPGA (so the l ip-l ops are automatically reset on power-up)
and the codeword assigned to the intended initial (reset) state is the all-zero codeword,
then reset will occur automatically.
2) On the
enum_encoding
and
fsm_encoding
attributes: As mentioned earlier, these
attributes can be used to select the desired encoding scheme (“sequential”, “one-hot”,
“001 011 010”, and others—see options in section 3.7), overriding the compiler's
