Hardware Reference
In-Depth Information
b) Regarding the outputs: The list of outputs (
output1
,
output2
, . . .) is the same in
all states (see lines 37-39, 48-50, . . .), and the output values (or expressions) are
always declared.
c) Regarding the next state: Again, the coverage is complete because all states (A, B,
C, . . .) are included, and in each state the declarations are i nalized with an
else
statement (lines 44, 55, . . .), guaranteeing that no condition is left unchecked.
Note 1:
See also the comments in sections 6.4, which show some template variations.
Note 2:
The VHDL 2008 review of the VHDL standard added the keyword
all
as a replace-
ment for a process' sensitivity list, so
process (all)
is now valid. It also added boolean
tests for
std_logic
signals and variables, so
if x='1' then . . .
can be replaced with
if x
then. . . .
Both are supported by the current version (12.1) of Altera's Quartus II compiler
but not yet by the current version (14.2) of Xilinx's ISE suite (XST compiler).
Note 3:
Another implementation approach, for simple FSMs, will be seen in chapter 15.
1 -------------------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 -------------------------------------------------------------
5 entity circuit is
6 generic (
7 param1: std_logic_vector(...) := <value>;
8 param2: std_logic_vector(...) := <value>);
9 port (
10 clk, rst: in std_logic;
11 input1, input2, ...: in std_logic_vector(...);
12 output1, output2, ...: out std_logic_vector(...);
13 end entity;
14 -------------------------------------------------------------
15 architecture moore_fsm of circuit is
16 type state is (A, B, C, ...);
17 signal pr_state, nx_state: state;
18 attribute enum_encoding: string; --optional, see comments
19 attribute enum_encoding of state: type is "sequential";
20 begin
21
22
--FSM state register:
23
process (clk, rst)
24
begin
25
if rst='1' then --see Note 2 above on boolean tests
26
pr_state <= A;
27
elsif rising_edge(clk) then
28
pr_state <= nx_state;
29
end if;
30
end process;
31
32
--FSM combinational logic:
33
process (all) --see Note 2 above on "all" keyword
34
begin
35
case pr_state is
