Hardware Reference
In-Depth Information
+V
DD
M
7
M
8
M
18
M
19
M
10
V
c
M
9
V
B3
M
12
I
Bsh
I
Bsh
M
21
M
14
M
16
Y
i
M
2
M
1
X
i
I
B1
Z
M
3
M
4
X
Y
M
11
M
13
I
SB
M
22
M
15
I
B
M
17
V
B2
I
B
M
20
V
B1
M
5
M
6
−V
SS
Fig. 4.6 CMOS realization of CCII+ (Adapted from [
48
]
©
2006 Springer)
4.6 A 1.5 V CMOS Current Conveyor Based on Wide
Range Transconductors
Madian et al. [
48
] presented a CCII+ architecture which uses two N-channel
differential pair instead of complimentary differential pairs for making the input
stage. This results in the availability of almost a rail-to-rail input and output
operation. Another advantage of this structure is that the number of current mirrors
required in the input stage is reduced. This circuit from [
48
] is shown in Fig.
4.6
.
Part of the circuit consisting of transistors M
1
-M
13
is essentially a wide band
transconductance circuit which has been converted into a voltage follower circuit
by adding the MOSFETs M
14
-M
20.
Finally, the complete CCII circuit is obtained
with the addition of two more transistors namely, M
21
and M
22
.
It has been shown that this architecture can be operated from a DC power supply
of
0.75 V with a total standby current of 133
ʼ
A.
4.7 High Speed High Precision Current Conveyors
Calvo et al. in [
43
] presented the design of a high speed high performance CMOS
current conveyor which was based upon a new high performance voltage follower
topology. The circuit proposed by them is shown in Fig.
4.7
. In this circuit,
MOSFET pair M
3,4
(M
7
,
8
) constitutes a complementary follower cascade whereas
the MOSFETs M
1,2
(M
5,6
) are two complementary level shifters. The positive
feedback path sampling the output current of M
7
(M
8
) and adjusting the bias current
of M
4
(M
3
) is implemented by transistors M
9
,
10, 17
(M
11
,
12, 18
). The current flowing
from node X is reproduced at node Z by the transistors M
13
,
14
(M
15
,
16
). Thus, a
high output impedance node and low voltage input node are created simultaneously.
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