Hardware Reference
In-Depth Information
+V
DD
I
B
I
B
M
8
I
z
I
x
V
x
X
V
y
Z
V
z
Y
M
1
M
2
V
B
M
7
M
6
−V
SS
M
4
M
5
M
3
−V
ss
−V
Fig. 4.5 Wide band CMOS current conveyor architecture proposed by Cha and Watanabe [
13
]
Y-input, the two current sources each equal to I
B
, assuming that M
3
,M
4
and M
5
are
matched, ensures I
z
¼
I
x
. By a routine circuit analysis, it is found that
g
m
1
g
m
2
R
X
v
X
¼
g
m
1
g
m
2
R
X
v
Y
ð
4
:
3
Þ
g
m
1
g
m
2
þ
If
g
m
1
¼
g
m
2
) then
v
x
exactly follows v
y
. Since no
current flows into node Y we have i
Y
¼0. The input impedance looking into the
node X is given by
g
m
2
or
g
m
1
g
m
2
R
x
>>
(
g
m
1
1
g
m
2
1
g
m
1
þ
1
g
m
2
g
m
3
r
ds
2
R
X
¼
ð
4
:
4
Þ
The input resistance R
x
can be made negligibly small by selecting the aspect ratios
of the MOSFETs M
1
and M
2
appropriately.
UsingMOS transistor model for a 1.2
ʼ
m standard CMOS process with dimensions
of M
1
,M
2
as 160/1.2
ʼ
m and 480/1.2
ʼ
m with all other NMOS transistors having
dimensions 120/2
ʼ
m, the current source design for I
B
¼
300
ʼ
A with supply voltages
of
2.5 V, the current transfer characteristic and voltage
transfer characteristic as well as the voltage gain between Z and Y port (with suitable
termination at ports X and Z) demonstrated a 3-dB bandwidth of more than 700 MHz.
5 V along with V
B
¼
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