Hardware Reference
In-Depth Information
C
1
C
2
I
LP
DVCC
DVCC
y
1
DVCC
y
1
z
1
z
1
z
1
y
1
1
2
I
BP
3
I
HP
V
in
y
2
y
2
y
2
z
2
z
2
z
2
x
x
x
I
in
V
NH
R
2
V
BP
R
3
V
LP
M
R12
M
R22
M
R32
R
1
R
3
M
R11
M
R21
M
R31
−V
c1
V
c1
−V
c2
V
c2
−V
c3
V
c3
Fig. 12.15 Mixed-mode KHN- biquad proposed by Minaei and Ibrahim (Adapted from [
17
]
©
2008 Wiley)
V
BP
V
i
¼
f
sR R
3
þ
ð
R
4
Þ=
R
1
C
1
R
3
R
4
g
C
1
R
1
R
4
ð
12
:
56
Þ
R
R
C
1
C
2
R
1
R
2
R
3
s
2
þ
s
þ
V
LP
V
i
¼
f
RR
3
þ
ð
R
4
Þ=
R
1
R
2
C
1
C
2
R
3
R
4
g
C
1
R
1
R
4
ð
12
:
57
Þ
R
R
C
1
C
2
R
1
R
2
R
3
s
2
þ
s
þ
From the above equations, the parameters
ˉ
0
and Q
0
can be obtained as:
r
R
C
1
C
2
R
1
R
2
R
3
r
R
1
C
1
RC
2
R
2
R
3
ω
0
¼
and Q
0
¼
R
4
ð
12
:
58
Þ
Hence, Q
0
can be controlled independently by R
4
.
Minaei-Ibrahim biquad In 2009, Minaei and Ibrahim proposed a mixed-mode
KHN-biquad using three DVCCs and five grounded passive elements suitable for
direct cascading [
17
]. Their circuit is shown here in Fig.
12.15
.
The filter circuit is capable of providing BPF, HPF and LPF responses simulta-
neously in CM operation and notch, BPF and LPF simultaneously in VM operation.
The notch and APF responses are also realizable by summing appropriate output
currents. Higher-order filters can be realized because of the low input and high
output impedance of the circuit for current signals and the high input and low output
impedance for the voltage signals. Assuming ideal DVCCs, an analysis of the
circuit of Fig.
12.15
gives the following transfer functions:
(i) CM operation (V
in
¼
0 (grounded)):
C
1
R
2
Ds
1
1
C
1
C
2
R
2
R
3
s
s
2
Ds
I
HP
I
in
¼
I
BP
I
in
¼
and
I
LP
I
in
¼
ð
12
:
59
Þ
ðÞ
;
ðÞ
Ds
ðÞ
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