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y
2
V
HP
V
BP
y
1
DVCC
z
y
1
DVCC
y
2
z
y
1
x
V
LP
z
DVCC
y
2
x
R
C
2
x
C
1
R
4
R
1
V
i
R
2
y
1
DVCC
y
2
z
x
R
3
Fig. 12.14 SIMO-type VM biquad filter proposed by Hassan and Mahmoud (Adapted from [
1
]
©
2008 Elsevier GmbH)
where
R
3
C
2
R
1
R
2
þ
1
C
1
C
2
R
1
R
2
s
2
Ds
ðÞ¼
þ
ð
12
:
53
Þ
Thus, LPF, BPF, HPF, notch and APF can be realized at V
01
,V
02
,V
03
,V
04
, and V
05
respectively. The expressions for
ˉ
0
and Q
0
are given by:
r
1
C
1
C
2
R
1
R
2
R
1
R
2
C
2
C
1
r
1
R
3
ω
0
¼
and Q
0
¼
ð
12
:
54
Þ
Hence,
ˉ
0
and Q
0
can be adjusted orthogonally. The configuration does not need
any component-matching conditions except for APF (R
3
¼
R
4
). To demonstrate the
workability of the proposed biquad filter PSPICE simulations were carried out
using CMOS realization of DVCC from [
204
] employing 0.35
μ
m CMOS process
parameters from TSMC.
Hassan-Mahmoud biquad Another high input impedance SIMO-type VM biquad
filter employing four DVCCs, two grounded capacitors and five grounded resistors
was proposed by Hassan and Mahmoud [
1
] which is shown here in Fig.
12.14
.
Assuming ideal DVCCs, the following VM transfer functions are determined
using a routine circuit analysis:
s
2
RR
3
þ
V
HP
V
i
¼
ð
R
4
Þ=
R
3
R
4
C
1
R
1
R
4
ð
12
:
55
Þ
R
R
C
1
C
2
R
1
R
2
R
3
s
2
þ
s
þ
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