Nonlinear Applications of CCs - Current Conveyors: Variants, Applications and Hardware Implementations - page 216

Fig. 8.4 Current control-
mirror based biasing
technique proposed by
Stiurca [ 5 ] 1995

+

I B

+

Q 1

Q 5

Q 2

A

Q 3

2A

R 0

Q 4

2A

R B

previously described designs. His proposition is shown in Fig. 8.4 . Another advan-
tage of this design is that the output offset voltage is easily adjustable to the desired
optimum level. The scheme of Fig. 8.4 should, in fact, be looked as an alternative
arrangement to those described in Fig. 8.3b for the rectifier architecture of Fig. 8.3a .
If we assume that the rectifying diodes are matched with the transistors in the
circuit of Fig. 8.4 , then the following equations apply:

V T ln I B 2 V T ln I B V T ln I D 2 V T ln I D =

2
I S þ I S þ 2 I S þ

I B R B ¼

I S þ

I D R L ð 8 : 1 Þ

If R L ¼ I B and therefore, the temperature independent DC

output offset voltage is obtained. The operation of this scheme in the rectifier circuit
of Fig. 8.3a was tested [ 5 ] through SPICE using full transistor level schematic of the
IC CC PA630. Simulations have confirmed that the use of this circuit results in a
rectifier with considerable improvements in terms of current consumption, temper-
ature stability, reduced output offset control as compared to schemes described
earlier
Khan et al. in [ 7 ] proposed the full wave rectifier circuit of Fig. 8.5 which
employs two CCII+ and is implementable with AD844. The circuit operation can be
explained as follows:
The current in the resistance R 1 is given by i xB ¼V in /(R 1 +2R x ) where R x is the
non-ideal input resistance looking into the terminal X of each CCII+. Now, using
the characterization of a CCII+, it follows that i zA ¼

R B , it follows that I D ¼

i xA . The diodes
D 1 -D 2 and D 3 -D 4 are so arranged that they would allow the Z-port output current to
flow either into the load resistance R L or to ground depending upon the polarity of
the input voltage V in .
WhenV in is positive the Z-output current of CCII+ A puts D 1 ON and D 2 OFF
thereby allowing current to flow in load R 2 , during the same condition, CCII+ B

i zB¼ i xB ¼