Link-Level Flow Control and Buffering - Microarchitecture of Network-on-Chip Routers - page 13

sender receiver

ready

valid

data

enq deq enq deq

Fig. 2.2 An elastic buffer attached at the sender and the receiver's interfaces

data_in data_out

FIFO
push

valid_in

ready_in

pop

full empty valid_out

ready_out

Fig. 2.3 An elastic buffer built around an abstract FIFO queue model

In an abstract form an EB can be built around a FIFO queue. An abstract FIFO
provides a push and a pop interface and informs its connecting modules when
it is full or empty. Figure 2.3 depicts how an abstract FIFO can be adapted to
the ready/valid protocol both in the upstream and the downstream connections.
The abstract FIFO model does not provide any guarantees on how a push to a
full queue or a pop from an empty queue is handled. The AND gates outside the
FIFO provide such protection. A push (write) is done when valid data are present
at the input of the FIFO and the FIFO is not full. At the read side, a pop (read)
occurs when the upstream channel is ready to receive new data and the FIFO is
not empty, i.e., it has valid data to send. In both sides of the EB we can observe
that a transfer to/from the FIFO occurs, when the corresponding ready/valid signals
are both asserted (as implemented by the AND gates in front of the push and pop
interfaces).

2.1.1 Half-Bandwidth Elastic Buffer

Using this abstract representation we can design EBs of arbitrary size. The simplest
form of an EB can be designed using one data register and letting the EB practically
act as a 1-slot FIFO queue. Besides the data register for each design we assume the
existence of one state flip-flop F that denotes if the 1-slot FIFO is Full (F

D 1) or

Empty (F 0). The state flip-flop actually acts as an R-S flip flop. It is set (S) when

the EB writes a new valid data (push) and it is reset (R) when data are popped out
of the 1-slot FIFO. Figure 2.4 depicts the organization of the primitive EB including
also its abstract VHDL description. The AND gates connecting the full/empty
signals of the EB and the incoming valid and ready signals are the same as in the
abstract implementation shown in Fig. 2.3 . Any R-S register can be implemented

D