Virtual-Channel Flow Control and Buffering - Microarchitecture of Network-on-Chip Routers - page 101

all VCs that have their main register full - will appear on the upstream channel
in the next clock cycle. The automatic data movement from the shared to main
buffer avoids any bubbles in the flow of flits of the same VC and achieves maximum
throughput.
ElastiStore should be considered as the equivalent of the primitive the 2-slot
EB used in the single-lane case where a main and an auxiliary HBEB are used for
allowing full transmission throughput. It allows the implementation of VC-based
flow control using close to the absolute minimum of one buffer slot per VC, without
sacrificing performance and without introducing any dependencies between VCs,
thus ensuring deadlock-free operation.

6.4 VC Flow Control on Pipelined Links

When the delay of the link exceeds the preferred clock cycle, one needs to segment
the link into smaller parts by inserting an appropriate number of pipeline stages. In
the case of single-lane channels, the role of the pipeline stages is covered by EBs,
which isolate the timing paths (all output signals - data, valid, and ready - are first
registered before being propagated in the forward or in the backward direction),
while still maintaining link-level flow control, as shown in Fig. 6.13 a, and discussed
in Sect. 2.5 . In the case of multi-lane channels that support VCs, we can achieve the
same result by replacing the EBs with the VC buffers of Fig. 6.5 or with ElastiStores
(see Fig. 6.13 b). Although this approach works correctly and allows for distributed
buffer placement, while still supporting VC-based flow control, it is not easily
handled in complex SoCs, since the addition of many registers (at least one for each
VC) in arbitrary positions, may create layout and physical integration problems.
Using VC buffers at the ends of the link and simple EBs on the link introduces
dependencies across VCs, since the flow control information per VC needs to be

a

data

valid
ready

Fig. 6.13 Pipelined links
with ( a ) EBs that support a
single-lane operation and
with ( b )EBsforalinkthat
supports multiple VCs. The
VC-based buffers distributed
on the link can be either
ElastiStores or baseline
buffers that use a separate
2-slot EB per VC

b

data

valid(0)
ready(0)

valid(1)
ready(1)