Virtual-Channel Flow Control and Buffering - Microarchitecture of Network-on-Chip Routers - page 102

serialized under a common ready/valid handshake; if one VC stops being ready,
all the words on the link should stop, irrespective of the VC they belong to. Such
dependencies ruin the isolation and deadlock-freedom properties of the VCs and
require ad-hoc modifications to the flow control mechanism.

6.4.1 Pipelined Links with VCs Using Ready/Valid Flow

Control

In the case of pipelined channels that employ ready/valid flow control for each
VC, we can rely on simple registers for pipelining the data and the ready/valid
handshakes signals on the link, as shown in Fig. 6.14 . In this case, the flits cannot
stop in the middle of the link, since the pipeline registers do not employ any flow
control. Many words may be in-flight, since it takes L f cycles for the signals
to propagate in the forward direction and L b cycles in the backward direction.
Therefore, the buffers at the receiver need to be sized appropriately to guarantee
lossless and full throughput operation. In the case of pipelined links, as also done in
the single-lane channels, any VC declares that it holds valid data after checking the
readiness of the corresponding downstream buffer, else multiple copies of the same
valid data will appear at the receiver's VC buffer.
First of all, assume that only one VC, i.e., the i th one, is active and the remaining
VCs do not send or receive any data. When the buffer of the i th VC is empty, it
asserts the ready(i ) signal. The sender will observe that ready(i ) is asserted after L b
cycles and immediately starts to send new data to that VC. The first flit will arrive
at the receiver after L f C L b cycles. This is the first time that the receiver can react
by possibly de-asserting the ready(i ) signal. If this is done, i.e., ready(i )=0, then
under the worst-case assumption, the receiver should be able to accept the L f 1
flits that are already on the link, plus the L b flits that may arrive in the next cycles
(the sender will be notified to stop with a delay of L b cycles). Thus, when the i th
VC stalls, it should have at least L f C L b empty buffers to ensure lossless operation.
Actually, the minimum number of buffers for the i th VC reduces to L f C L b 1,
if we assume that the sender stops transmission in the same cycle it observes that

Lb registers

ready

...

control

update

valid

...

...

VC buffers

data

Lf registers

sender receiver

Fig. 6.14 Abstract model of a pipelined link with multiple VCs and independent ready/valid
handshake signals per VC