SystemVerilog Language Overview - SVA: The Power of Assertions in SystemVerilog - page 41

...
a2: assert property (@( posedge clk) req_granted(rq, done));
...
endmodule :m
It is also possible to import all the names defined in the package common_props
into module m using the wild card notation:
module m( input logic rq, done, clk, ...);
import common_props:: * ;
wire [7:0] data;
...
a1: assert final (one_cold(data));
...
a2: assert property (@( posedge clk) req_granted(rq, done));
...
endmodule :m
The latter version looks more convenient, but the wild card notation may lead to
a clutter with the local name space and with namespaces of other packages when
multiple wild card imports are used. t

Exercises

2.1. What are the sizes of wires x and y ?
'define a3+5
module m (...);
let b=3+5;
wire ['a * 4] x;
wire [b * 4] y;
...
endmodule :m
What will happen if the statement let b=3+5; has been substituted by
int b=3+5; ?
2.2.

What is wrong with the following code?

module m( input logic a, b, c, clk, output logic x, y, z);
initial begin
y = 1'b0;
z = 1'b0;
end
always_comb x=a&b;
always_latch y=a|c;
always_ff @( posedge clk) begin
if (y)x<=a;
@( posedge clk)x<=x&b;
end
final @( posedge clk)z<=x|y;
endmodule :m