SystemVerilog Language Overview - SVA: The Power of Assertions in SystemVerilog - page 40

Example 2.12. A package is a natural container for common let declarations,
sequences, properties and checkers to be used project-wide, such as the package
common_props shown below.
package common_props;

let one_cold(sig) = $onehot(~sig);

property req_granted ( sequence req, property gnt);
req |=> gnt;
endproperty : req_granted
...
endpackage : common_props
In this package it is shown a let declaration for one cold encoding of the bits
of sig , and a property declaration to check that the request req is granted ( gnt is
received) in the next clock cycle. In order for the property to be generic, req and
gnt are not limited to signals, but req may be an arbitrary sequence, and gnt may
be an arbitrary property (see Sect. 6.4 ).

t

To reference a declaration from a package one has to provide the package name
followed by :: within the name declared in the package.
Example 2.13. The code below shows how to use declarations from the package
common_props from Example 2.12 .
module m( input logic rq, done, clk, ...);
wire [7:0] data;
...
a1: assert final (common_props::one_cold(data));
...
a2: assert property (@( posedge clk)
common_props::req_granted(rq, done));

...
endmodule :m
In module m the let and the property names from the package are prefixed with
the package name common_props:: .

t

To make specific names declared in a package visible in the current scope,
one can use an import statement containing the list of names to be referenced.
Alternatively, one can use a wild card import to make all construct names belonging
to the package visible in the current scope.

Example 2.14. Instead of explicit specification of the name of package
common_props defined in Example 2.12 one can use an import statement in module
m from Example 2.13 :
module m( input logic rq, done, clk, ...);
import common_props::one_cold, common_props::req_granted;
wire [7:0] data;
...
a1: assert final (one_cold(data));