Hardware Reference
In-Depth Information
2.3.
Correct the following code to make it legal.
module
m(
input logic
a, b, c,
output logic
o);
if
(a)o=b;
else
o=c;
endmodule
:m
2.4.
What is illegal in the following code?
module
m(
input logic
a, b, clk);
clocking
mycblk @(
posedge
clk);
property
p; a |=> b;
endproperty
a1:
assert property
(p);
endclocking
a2:
assert property
(p);
endmodule
:m
2.5.
What is the purpose of the following SystemVerilog design elements?
module
interface
program
checker
package
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