SystemVerilog Language Overview - SVA: The Power of Assertions in SystemVerilog - page 32

These procedures follow the same syntax as general always procedure though
several limitations apply.

2.2.1.1 Procedure always_comb

The always_comb procedure is intended to represent combinational logic. It has
an implicit sensitivity list including all variables read within the block or within
functions called from this block. The always_comb procedure is automatically
executed at time 0 to have its outputs consistent with its inputs. Consult the LRM
for other rules and restrictions imposed on the always_comb procedure.
Example 2.3.

The following code illustrates a mux implementation using

always_comb .
logic in1, in2, sel, out;
always_comb
if (sel) out = in2;
else out = in1;
The signal out cannot be assigned anywhere else in the code because it is
assigned within an always_comb procedure.

t

2.2.1.2 Procedure always_latch

The always_latch procedure is intended to represent latched logic. From the
formal point of view there is no difference between the always_comb and
always_latch procedures, and the appropriate procedure should be chosen to
clarify the design intent. However, the tools may impose additional checks. For
example, unlike always_latch , they may enforce that the variables assigned inside
always_comb are fully assigned.
Example 2.4. The following code illustrates a latch implementation using
always_latch .
logic data, clk, q;
always_latch
if (clk) q = data;
The signal q cannot be assigned anywhere else in the code because it is assigned
inside an always_latch procedure. t

2.2.1.3 Procedure always_ff

The always_ff procedure is intended to represent sequential logic, such as flip-
flops and registers. Unlike the general always procedure, the always_ff procedure
contains exactly one event control and no blocking timing controls (such as delay