SystemVerilog Language Overview - SVA: The Power of Assertions in SystemVerilog - page 33

control # ). Similar to always_comb and always_latch , it is illegal to modify
signals assigned in this procedure from any other place. Consult the LRM for other
restrictions imposed on the always_ff procedure.
Example 2.5. The following code illustrates a flip-flop implementation using

always_ff .
logic data, q, clk, rst;
always_ff @( posedge clk or negedge rst)
if (!rst) q <= 1'b0;
else q <= data;
The signal q cannot be assigned anywhere else in the code because it is assigned
inside an always_ff procedure.

t

2.2.2 Final Procedure

The final procedure is the opposite of the initial procedure. It executes at the
end of the simulation. Often it is used as a clean-up routine and for displaying or
storing information such as simulation final results, statistics, and coverage data.
The users can declare more than one final procedure, in which case, they are
executed sequentially, but in an arbitrary order. 1 Effectively, the final procedures
constitute a single process in which the procedures execute sequentially. Because
the final procedure executes in zero time, the statements allowed in a final procedure
are those allowed in a function. Consult the LRM for an exact description of the final
procedure.

Example 2.6. The following code illustrates the use of the final procedure to display
the total number of assertion failures.

logic clk, rdy, rst;
int fCount = 0;
...
always @( posedge clk)
rdy_fail: assert (rdy -> !rst) else fCount++;
final
$display("Number of assertions rdy_fail failed: %d",fCount);
Assertion rdy_fail increments fCount each time it fails. At the end of
simulation, the final procedure prints the total number of the assertion rdy_fail
failures. t

1 SystemVerilog LRM suggests that the order of execution for final procedures be deterministic for
a tool.