SystemVerilog Language Overview - SVA: The Power of Assertions in SystemVerilog - page 31

Example 2.2. Generate if and procedural if . Consider the following module

declaration:

1 module m#( bit FLAG = 1) ( input logic in1, in2, select,
2 output logic out1, out2);
3 if (FLAG) assign out1 = in1;
4 else assign out1 = in2;
5 always_comb
6 if (select) out2 = in1;
7 else out2 = in2;
8 endmodule :m

In this example the if statement on Line 3 is a generate if , because an if
outside a procedural context is recognized as generate. This statement is processed
at elaboration time using the value of FLAG , which is a module parameter. An attempt
to put a non-constant expression, such as select , in this case is illegal.
The if statement on Line 6 is a normal procedural if statement. It is executed at
simulation time, and its argument need not to be an elaboration time constant. The
procedural if statement is recognized by its procedural context of the always_comb
procedure. t

2.2 SystemVerilog Procedures

Most SystemVerilog design elements (modules, interfaces, programs and checkers)
can contain structured procedures , previously called procedural blocks . There
are the following structured procedures in SystemVerilog: initial, always and
final procedures, functions and tasks. Some design elements have limitations on
the procedures they may contain. For example, programs cannot contain always
procedures; packages can contain no procedures.
Initial and general purpose always procedures are well-known and are not
discussed here. We will limit our consideration by outlining specialized always
procedures and by final procedures.

2.2.1 Specialized Always Procedures

In SystemVerilog there are several specializations of always procedures:

￿ always_comb
￿ always_latch
￿ always_ff