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perform syntactic and semantic analysis and to check for syntax or semantics errors.
The source files can be compiled all at once or divided into multiple sets of files so
that each set can be compiled separately into what is known as a
compilation unit
.
Typically, for simulation the compilation is performed by a separate tool, called a
compiler
. This allows compiling the SystemVerilog model only once and checking
it multiple times on different tests. Some simulators, however, contain a compiler as
their integral part and perform compilation anew for each simulation session.
To build the final simulation model, all compilation units together must go
through the
elaboration
phase which binds all components by evaluating parameter
values and constant expressions, connecting instances, building hierarchies, and
resolving references. For noninterpretive simulators, another step is needed to create
object code from the elaborated model to build the final executable simulation
model.
It is important to distinguish between the computations performed at compile
time, elaboration time and simulation time. For example, compiler directives,
such as
'include
,
'define
and
'ifdef
are evaluated at compile time. As
stated above, evaluation of constant expressions, including parameter evaluation is
done at elaboration time. The same is true for generate constructs. On the other
hand, assignment statements and procedural control statements are evaluated at
simulation time. We clarify the difference between compile time, elaboration time
and simulation time constructs with the following examples.
Example 2.1.
Consider the following statements:
'define
k2+3
let
m=2+3;
int
n=2+3;
All of them seem very similar, and all of them evaluate to 5, but their evaluation
time is different, and so is their semantics. Namely,
k
is evaluated at compile time,
m
is evaluated at elaboration time, and
n
is evaluated at simulation time.
The declarations
logic
['k:0] a;
and
logic
[m:0] a;
are legal, but
logic
[n:0] a;
is not, because the bounds of a vector must be known at the
elaboration time.
The statement
'ifdef
k
is legal, but both
'ifdef
m
and
'ifdef
n
are illegal,
because
'ifdef
requires a macro identifier.
Note also that the compile time definition is processed syntactically whereas
elaboration time and simulation time constructs are evaluated semantically. For
example,
logic
[2
*
'k:0] a;
is equivalent to
logic
[7:0] a;
because
2
*
'k
is
substituted literally by
2
*
2+3
(therefore, it is recommended to put parentheses in
the
'define
statement:
'define
k(2+3)
). But
logic
[2
*
m:0] a;
is equiva-
lent to
logic
[10:0] a;
, because the evaluation is done at elaboration time, and
the values of
m
is first evaluated to 5, and only then it is multiplied by 2. For a
more detailed discussion on the differences between
'define
and
let
statements
see Sect.
8.1
.
t
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