SystemVerilog Language Overview - SVA: The Power of Assertions in SystemVerilog - page 29

Chapter 2
SystemVerilog Language Overview

The limits of my language mean the limits of my world.
— Ludwig Wittgenstein

Our objective in this chapter is to provide an overview of some SystemVerilog
features that are important for understanding assertions, needed for writing asser-
tions, or used in conjunction with assertions to support other tasks. The System-
Verilog features common with Verilog are considered known and are not discussed
in this chapter.
We begin this chapter with a discussion about compilation and elaboration. Then
we provide a brief overview of several SystemVerilog constructs that are not part of
Verilog, and therefore may be not commonly known, but are referred later in this
topic. These constructs include structured procedures, clocking blocks, interfaces,
programs and packages. The SVA-related constructs, such as checkers are not
considered in this section, because they are studied in detail in next chapters.
The reader familiar with the material described here may safely skip this
chapter. A detailed description of SystemVerilog language, of testbench writing,
methodology and design is out of the scope of this topic and can be found in the
topics [ 16 , 30 , 59 , 61 , 64 ]. The SystemVerilog Language Reference Manual [ 8 ]
(referred in the rest of this topic as LRM) is, of course, the most comprehensive
reference.

2.1 Compilation and Elaboration

SystemVerilog code, prior to be simulated or formally verified by a tool, needs to be
preprocessed and loaded. This initial step is divided into two major phases: compi-
lation and elaboration. The goal of compilation is to read one or more source files, to