Assertion Statements - SVA: The Power of Assertions in SystemVerilog - page 87

Immediate Coverage. The immediate coverage statement acts like an if statement:
when the body expression is true, the pass action is performed. For example,
the following statement prints a message each time when the counter reaches its
maximal value:

c1: cover (ctr_max) $display("Counter reached its maximal
value");

Deferred Coverage. Deferred coverage is similar to immediate coverage, but it is
glitch-free (see Sect. 4.3 ). In the following example, the message is issued each time
the bus is active. It uses observed deferred cover, but it could also be a final observed
cover if glitches spanning entire time slots should be filtered out. bus_drivers is a
vector of wires driving the bus:

wire [15:0] bus_drivers;
c2: cover #0 (bus_drivers !== 16'bz) $display("Bus is active");
If a final deferred cover is used, the recording of hits in a coverage database by
the simulator would have to take place in the postponed region. The LRM is not
clear whether a change of state of a database is permitted in this region, even though
it does not generate or schedule any event.

4.7.2.1 Concurrent Coverage

There are two versions of concurrent coverage: property coverage and sequence
coverage. Property coverage has the keyword cover property , and its body may
contain an arbitrary property, as concurrent assertions and assumptions.

property_coverage_body ::=
[clocking_event] [ disable iff ( reset ) ] property

If an evaluation attempt is successful, the pass action is executed only once for
each evaluation attempt.
The

sequence coverage has the similar syntax, but it has the keyword

cover sequence instead

of cover property , and its body is limited to

a sequence. 10

sequence_coverage_body ::=
[clocking_event] [ disable iff ( reset ) ] sequence

Here, the pass action is executed at each sequence match.
The example in Fig. 4.16 illustrates the difference between the two forms.
The body of both statements is identical, the intention is to cover a scenario
when write followed by several (maybe zero) busy cycles is followed by a read .
But their behavior is different. For the trace shown in Table 4.1 c3 reports the hit

10 See Chap. 6 .