Assertion Statements - SVA: The Power of Assertions in SystemVerilog - page 88

Fig. 4.16 Concurrent coverage

Table 4.1 Stimuli for c3

Clock cycle write busy read

and c4

t 1 0 0

t C 1 0 1 0

t C 2 0 1 1

t C 3 0 0 1

only once per attempt—at time t C 2, while c4 reports the hit twice—at times t C 2
and t C 3.
In practice, property coverage is much more useful than sequence coverage. The
main use of sequence coverage is to react on each sequence match in the pass action
block to trigger some testbench actions.

For functional coverage collection use cover property statements.

4.7.3 Checking Coverage

Usually coverage is checked in simulation, but there is an added value to check
coverage in FV too.

4.7.3.1 Checking Coverage in Simulation

Checking coverage in simulation is somewhat similar to checking transaction
completion for assertions—the simulator reports when a given sequence of signals
happens. For example, for the cover statement

cover property (@( posedge clk) write ##1 read);
the simulator will report each time it detects write signal followed by read .
The simulators usually register successful completion of evaluation attempts in a
coverage database and collect the coverage statistics across available tests.