Assertion Statements - SVA: The Power of Assertions in SystemVerilog - page 86

4.7 Coverage

The last assertion statement cover has also been mentioned in previous chapters.
In this section, we provide general information about cover statements, while the
detailed discussion about coverage can be found in Chap. 18 .

4.7.1 Motivation

Assertions and assumptions define how the DUT and its environment must behave.
It is also highly desirable to document how they can behave. When testing the
design, it is necessary to make sure that the tests cover important scenarios, and
different corner cases. This is achieved by functional coverage —a methodology to
specify the scenarios to be covered. For example, for the model shown in Fig. 4.13
it is useful to check the following scenarios:

￿ read is asserted.
￿ write is asserted.
￿Both read and write are simultaneously deasserted.
The corresponding coverage statements are shown on Fig. 4.15

4.7.2 Coverage Definition

Cover statement is used to register when a specific scenario happens in the design.
It has the following syntax:

cover_statement ::= name : cover_keyword ( cover_body ) pass_action

Unlike assertions and assumptions, coverage statements have only pass action
which is executed when the coverage condition (scenario) is met. The corresponding
statistical information is reported by a simulator and is registered in the coverage
database. Like assertions and assumptions, coverage statements may be immediate,
deferred (observed and final), and concurrent.

Fig. 4.15 Coverage statements for simple RAM