Hardware Reference
In-Depth Information
Figure 1.14
Internal architecture of the 8255A
(ii) Ascertain whether the successful request has a higher priority than the
level currently being serviced.
(iii) If the condition in (ii) is satisfied, issue an interrupt to the processor
by asserting the active high INT line.
(d) The processor acknowledges the interrupt signal and responds by pulsing
the interrupt acknowledge (INTA) line.
(e) Upon receiving the INTA pulse from the processor, the highest priority ISR
bit is set and the corresponding IRR bit is reset.
(f) The processor then initiates a second interrupt acknowledge (INTA) pulse.
During this second period for which the INTA line is taken low, the 8259
outputs a pointer on the data bus which is then read by the processor.
The pin connections for the 8259A are shown in Figure 1.13.
8284A Clock generator
The 8284A is a single chip clock generator/driver designed specifically for use
by the 8086 family of devices. The chip contains a crystal oscillator, divide-by-3
