Hardware Reference
In-Depth Information
Table 1.10 Port addresses (hexadecimal) used in the PC family
Device
PC-XT
PC-AT
8237A DMA Controller
000-00F
000-01F
8259A Interrupt Controller
020-021
020-03F
8253/8254 timer
040-043
040-05F
8255 Parallel Interface
060-063
n.a.
8042 keyboard controller
n.a.
060-06F
DMA page register
080-083
080-09F
NMI mask register
0A0-0A7
070-07F
Second 8259A Interrupt Controller
n.a.
0A0-0BF
Second 8237A DMA Controller
n.a.
0C0-0DF
Maths Coprocessor (8087, 80287)
n.a.
0F0-0FF
Games controller
200-20F
200-207
Expansion unit
210-217
n.a.
Second parallel port
n.a.
278-27F
Second serial port
2F8-2FF
2F8-2FF
Prototype card
300-31F
300-31F
Fixed (hard) disk
320-32F
1F0-1F8
First parallel printer
378-37F
378-37F
SDLC adapter
380-38F
380-38F
BSC adapter
n.a.
3A0-3AF
Monochrome adapter
3B0-3BF
3B0-3BF
Enhanced graphics adapter
n.a.
3C0-3CF
Colour graphics adapter
3D0-3DF
3D0-3DF
Floppy disk controller
3F0-3F7
3F0-3F7
First serial port
3F8-3FF
3F8-3FF
counter, ready, and reset logic. On the original PC, the quartz crystal is a series
mode fundamental device which operates at a frequency of 14.312818 MHz.
The output of the divide-by-3 counter takes the form of a 33% duty cycle square
wave at precisely one-third of the fundamental frequency (i.e. 4.77 MHz). This
signal is then applied to the processor's clock (CLK) input. The clock generator
also produces a signal at 2.38 MHz which is externally divided to provide a
5.193 MHz 50% duty cycle clock signal for the 8253 Programmable Interval
Timer (PIT).
8288 Bus Controller
The 8288 Bus Controller decodes the status outputs from the CPU (S0 and
S1) in order to generate the requisite bus command and control signals. These
signals are used as shown in Table 1.11. The 8288 issues signals to the sys-
tem to strobe addresses into the address latches, to enable data onto the
buses, and to determine the direction of data flow through the data buffers.
The
internal
architecture
and
pin
connections
for
the
8288
are
shown
in
Figure 1.13.
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