Hardware Reference
In-Depth Information
Table 1.9
Truth table for the 8253
CS
RD
WR
A1
A0
Function
0
1
0
0
0
Load counter 0
0
1
0
0
1
Load counter 1
0
1
0
1
0
Load counter 2
0
1
0
1
1
Write mode word
0
0
1
0
0
Read counter 0
0
0
1
0
1
Read counter 1
0
0
1
1
0
Read counter 2
0
0
1
1
1
No-operation (tri-state)
1
x
x
x
x
Disable tri-state
0
1
1
x
x
No-operation (tri-state)
8255A Programmable Peripheral Interface
The 8255A Programmable Peripheral Interface (PPI) is a general purpose I/O
device which provides no less than 24 I/O lines arranged as three 8-bit I/O
ports. The pin connections and internal architecture of the 8255A are shown in
Figures 1.13 and 1.14, respectively. The Read/Write and Control Logic block
manages all internal and external data transfers. The port addresses used by the
8255A are given in Table 1.10.
The functional configuration of each of the 8255's three I/O ports is fully pro-
grammable. Each of the control groups accepts commands from the Read/Write
Control Logic, receives Control Words via the internal data bus, and issues the
requisite commands to each of the ports. At this point, it is important to note
that the 24 I/O lines are, for control purposes, divided into two logical groups
(A and B). Group A comprises the entire eight lines of Port A together with the
four upper (most significant) lines of Port B. Group B, on the other hand, takes
in all eight lines from Port B together with the four lower (least significant)
lines of Port C. The upshot of all this is simply that Port C can be split into two
in order to allow its lines to be used for status and control (handshaking) when
data is transferred to or from Ports A or B.
8259A Programmable Interrupt Controller
The 8259A Programmable Interrupt Controller (PIC) was designed specifically
for use in real-time interrupt driven microcomputer systems. The device man-
ages eight levels of request and can be expanded using further 8259A devices.
The sequence of events which occurs when an 8259A device is used in
conjunction with an 8086 or 8088 processor is as follows:
(a)
One or more of the interrupt request lines (IR0-IR7) are asserted (note that
these lines are active high) by the interrupting device(s).
(b)
The corresponding bits in the IRR register become set.
(c)
The 8259A evaluates the requests on the following basis:
(i)
If more than one request is currently present, determine which of the
requests has the highest priority.
