Hardware Reference
In-Depth Information
Figure 1.13
Pin connections for legacy support chips
Word Register. The down counters are negative edge triggered such that, on a
falling clock edge, the contents of the respective counter is decremented.
The three counters are fully independent and each can have separate mode
configuration and counting operation, binary or BCD. The contents of each
16-bit count register can be loaded or read using simple software referencing
the relevant port addresses shown in Table 1.10. The truth table for the chip's
active low chip select (CS), read (RD), write (WR) and address lines (A1 and
A0) is shown in Table 1.9.
