Hardware Reference
In-Depth Information
8237A Direct Memory Access Controller
The 8237A DMA Controller (DMAC) can provide service for up to four inde-
pendent DMA channels, each with separate registers for Mode Control, Current
Address, Base Address, Current Word Count, and Base Word Count. The
DMAC is designed to improve system performance by allowing external devices
to directly transfer information to and from the system memory. The 8237A
offers a variety of programmable control features to enhance data throughput
and allow dynamic reconfiguration under software control.
The 8237A provides four basic modes of transfer: Block, Demand, Single
Word, and Cascade. These modes may be programmed as required, however,
channels may be auto-initialize to their original condition following an End Of
Process (EOP) signal.
The 8237A is designed for use with an external octal address latch such as the
74LS373. A system's DMA capability may be extended by cascading further
8237A DMAC chips and this feature is exploited in the PC-AT which has two
such devices.
The least significant four address lines of the 8237A are bi-directional: when
functioning as inputs, they are used to select one of the DMA controllers' 16
internal registers. When functioning as outputs, on the other hand, a 16-bit
address is formed by taking the eight address lines (A0 to A7) to form the least
significant address byte whilst the most significant address byte (A8 to A15)
is multiplexed onto the data bus lines (D0 to D7). The requisite address latch
enable signal (ADSTB) is available from pin-8. The upper four address bits (A16
to A19) are typically supplied by a 74LS670 4
4 register file. The requisite
bits are placed in this device (effectively a static RAM) by the processor before
the DMA transfer is completed.
DMA channel 0 (highest priority) is used in conjunction with the 8253 Pro-
grammable Interval Timer (PIT) in order to provide a memory refresh facility
for the PC's dynamic RAM. DMA channels 1-3 are connected to the expansion
slots for use by option cards.
The refresh process involves channel 1 of the PIT producing a negative going
pulse with a period of approximately 15
ยต
s. This pulse sets a bistable which,
in turn, generates a DMA request at the channel-0 input of the DMAC (pin-
19). The processor is then forced into a wait state, and the address and data
bus buffers assume a tri-state (high impedance) condition. The DMAC then
outputs a row refresh address and the row address strobe (RAS) is asserted.
The 8237 increments its refresh count register and control is then returned to
the processor. The process then continues such that all 256 rows are refreshed
within a time interval of 4 ms. The pin connections for the 8237A are shown in
Figure 1.13.
8253 Programmable Interval Timer
The 8253 is a Programmable Interval Timer (PIT) which has three independent
presettable 16-bit counters each offering a count rate of up to 2.6 MHz. The pin
connections for the 8253 are shown in Figure 1.13. Each counter consists of a
single 16-bit presettable down counter. The counter can function in binary or
BCD and its input, gate, and output are configured by the data held in the Control
