Digital Signal Processing Reference
In-Depth Information
band.
14.5 Filter realizat
ion
In the preceding chapters, we presented several different techniques to calculate
the output of a DT system. In the time domain, the output response
y
[
k
] can be
determined from its input
x
[
k
] either by solving a linear, constant-coefficient,
difference equation of the following form:
a
0
y
[
k
]
+
a
1
y
[
k
−
1]
++
a
N
y
[
k
−
N
]
=
b
0
x
[
k
]
+
b
1
x
[
k
−
1]
++
b
M
x
[
k
−
M
]
or, alternatively, by calculating the convolution sum between the input
x
[
k
] and
the impulse response
h
[
k
]. The convolution sum is given by
∞
y
[
k
]
=
x
[
k
]
∗
h
[
k
]
=
x
[
m
]
h
[
k
−
m
]
.
m
=−∞
In the frequency domain, the convolution property is used to express the con-
volution sum in terms of the transfer function
H
(
Ω
) and the CTFT
X
(
Ω
) of the
input as follows:
Y
(
Ω
)
=
X
(
Ω
)
H
(
Ω
)
,
x
[
k
]
z
−1
x
[
k
− 1]
from which the output
y
[
k
] can be determined by calculating the inverse CTFT
of
Y
(
Ω
). On digital computers and specialized DSP boards, the output of a dig-
ital filter is generally obtained by iteratively evaluating the recurrence formula,
y
[
k
]
=−
1
(a)
+
x
1
[
k
]
x
1
[
k
] +
x
2
[
k
]
a
0
(
+
a
1
y
[
k
−
1]
++
a
N
y
[
k
−
N
])
x
2
[
k
]
1
a
0
(
b
0
x
[
k
]
+
b
1
x
[
k
−
1]
++
b
M
x
[
k
−
M
])
,
+
(b)
a
x
[
k
]
ax
[
k
]
derived from the difference equation. Implementing the recurrence formula
requires delaying the samples of the input and output sequences, multiplying
the sample values with constant coefficients, and adding the resulting prod-
ucts. In other words, we require three mathematical operations, shift or delay,
multiplication, and addition, to solve a difference equation iteratively. In the fol-
lowing, we introduce the schematic representation of these three fundamental
operations.
(c)
Fig. 14.12. Fundamental
elements for building digital
implementations for FIR and IIR
filters. (a) Unit delay element;
(b) adder; (c) constant-
coefficient multiplier.
14.5.1 Shift or delay operator
On digital computers and specialized DSP boards, the shift operation is
implemented using a cascaded combination of delay elements. The schematic
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