Digital Signal Processing Reference
In-Depth Information
h
[
k
] of the unit delay element is given by
h
[
k
]=
δ
[
k
- 1]. The output is there-
fore given by
x
[
k
]
∗ δ
[
k
−
1]
=
x
[
k
−
1]. If a delay of more than one sample
is required, several unit delay elements may be cascaded together in a series
configuration.
14.5.2 Adder
On digital devices, adders are typically implemented using combinational or
sequential circuits consisting of registers and logic gates. The schematic repre-
sentation of an adder is illustrated in Fig. 14.12(b), where the input sequences
x
1
[
k
] and
x
2
[
k
] produce an output
x
1
[
k
]
+
x
2
[
k
].
14.5.3 Multiplication by a constant
On digital devices, multipliers are typically implemented using sequential cir-
cuits consisting of registers, shift delays, and logic gates. The schematic rep-
resentation of a constant multiplier is shown in Fig. 14.12(c), where the input
sequence
x
[
k
] is multiplied with a constant
a
, producing an output
ax
[
k
].
In the following sections, we sketch signal flow graphs for efficient implemen-
tations of both FIR and IIR digital filters using the aforementioned elements,
referred to as the fundamental elements. By manipulating the signal flow graphs,
we present several different but equivalent structures for the same transfer func-
tion. We also demonstrate the effect of finite-precision arithmetic on the gain-
frequency characteristics of digital filters, and provide several design tips to
alleviate the problems arising from finite-precision arithmetic.
14.6 FIR filters
A causal FIR filter, of finite length
N
and having non-zero values in the range
0
≤
k
≤
(
N
−
1), is represented by the following transfer function:
N
−
1
h
[
k
]
z
−
k
=
h
[0]
+
h
[1]
z
−
1
+
h
[2]
z
−
2
++
h
[
N
−
1]
z
−
(
N
−
1)
H
(
z
)
=
k
=
0
(14.14)
or, alternatively by a difference equation obtained by solving the convolution
sum:
N
−
1
y
[
k
]
=
h
[
k
]
x
[
k
−
m
]
m
=
0
=
h
[0]
x
[
k
]
+
h
[1]
x
[
k
−
1]
++
h
[
N
−
1]
x
[
k
−
(
N
−
1)]
.
(14.15)
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