References - Computer Architecture: A Quantitative Approach - page 723

448. Palmer J, Morse S. The 8087 Primer New York: John Wiley & Sons; 1984; 93.
449. Pan S-T, So K, Rameh JT. Improving the accuracy of dynamic branch prediction using
branch correlation. Proc Fifth Int'l Conf on Architectural Support for Programming Languages
and Operating Systems (ASPLOS) 1992;76-84.
450. Partridge C. Gigabit Networking Reading, Mass: Addison-Wesley; 1994.
451.

Paterson D. Reduced instruction set computers. Communications of the ACM .

1985;28(1):8-21 (January).
452. Paterson D. Latency lags bandwidth. Communications of the ACM . 2004;47(10):71-75 (Octo-
ber).
453. Paterson DA, Dizel DR. The case for the reduced instruction set computer. Computer Ar-
chitecture News . 1980;8(6):25-33 (October).
454. Paterson DA, Hennessy JL. Computer Organization and Design: The Hardware/Software
Interface 3rd ed. San Francisco: Morgan Kaufmann; 2004.
455. Paterson, D. A., G. A. Gibson, and R. H. Kaz [1987]. A Case for Redundant Arrays of Inex-
pensive Disks (RAID) , Tech. Rep. UCB/CSD 87/391, University of California, Berkeley. Also
appeared in Proc. ACM SIGMOD , June 1-3, 1988, Chicago, 109-116.
456. Paterson DA, Garrison P, Hill M, et al. Architecture of a VLSI instruction cache for a RISC.
10th Annual Int'l Conf on Computer Architecture Conf Proc. 1983;108-116.
457. Pavan P, Bez R, Olivo P, Zanoni E. Flash memory cells—an overview. Proc IEEE .
1997;85(8):1248-1271 (August).
458. Peh LS, Dally WJ. A delay model and speculative architecture for pipe-lined routers. Proc
7th Int'l Symposium on High-Performance Computer Architecture 2001.
459. Peng V, Samudrala S, Gavrielov M. On the implementation of shifters, multipliers, and
dividers in VLSI floating point units. Proc 8th IEEE Symposium on Computer Arithmetic
1987;95-102.
460. Pfister GF. In Search of Clusters 2nd ed. Upper Saddle River, N.J.: Prentice Hall; 1998.
461. Pfister GF, Brantley WC, George DA, et al. The IBM research parallel processor prototype
(RP3): Introduction and architecture. Proc 12th Annual Int'l Symposium on Computer Archi-
tecture (ISCA) 1985;764-771.
462. Pinheiro E, Weber WD, Barroso LA. Failure trends in a large disk drive population. Proc 5th
USENIX Conference on File and Storage Technologies (FAST '07) 2007.
463. Pinkston TM. Deadlock characterization and resolution in interconnection networks. In:
Zhuand MC, Fanti MP, eds. Deadlock Resolution in Computer-Integrated Systems . Boca Raton,
FL: CRC Press; 2004;445-492.
464. Pinkston TM, Shin J. Trends toward on-chip networked microsystems. Int'l J of High Per-
formance Computing and Networking . 2005;3(1):3-18.
465. Pinkston TM, Warnakulasuriya S. On deadlocks in interconnection networks. 24th Annual
Int'l Symposium on Computer Architecture (ISCA) 1997.
466. Pinkston TM, Benner A, Krause M, Robinson I, Sterling T. InfiniBand: The 'de facto' future
standard for system and local area networks or just a scalable replacement for PCI buses?
Cluster Computing (special issue on communication architecture for clusters) . 2003;6(2):95-104
(April).
467. Postiff MA, Greene DA, Tyson GS, Mudge TN. The limits of instruction level parallelism in
SPEC95 applications. Computer Architecture News . 1999;27(1):31-40 (March).
468. Przybylski SA. Cache Design: A Performance-Directed Approach San Francisco: Morgan
Kaufmann; 1990.
469. Przybylski SA, Horowiz M, Hennessy JL. Performance trade-ofs in cache design. 15th An-
nual Int'l Symposium on Computer Architecture 1988;290-298.