References - Computer Architecture: A Quantitative Approach - page 724

470. Puente V, Beivide R, Gregorio JA, Prellezo JM, Duato J, Izu C. Adaptive bubble router: A
design to improve performance in torus networks. Proc 28th Int'l Conference on Parallel Pro-
cessing 1999.
471. Radin G. The 801 minicomputer. Proc Symposium Architectural Support for Programming Lan-
guages and Operating Systems (ASPLOS) 1982;39-47.
472. Rajesh Bordawekar, Uday Bondhugula, Ravi Rao: Believe it or not!: mult-core CPUs can
match GPU performance for a FLOP-intensive application! 19th International Conferen-
ce on Parallel Architecture and Compilation Techniques (PACT 2010), Vienna, Austria,
September 11-15, 2010: 537-538.
473. Ramamoorthy CV, Li HF. Pipeline architecture. ACM Computing Surveys . 1977;9(1):61-102
(March).
474. Ranganathan P, Leech P, Irwin D, Chase J. Ensemble-Level Power Management for Dense
Blade Servers. Proc 33rd Annual Int'l Symposium on Computer Architecture (ISCA) 2006;66-77.
475. Rau BR. Iterative modulo scheduling: An algorithm for software pipelining loops. Proc 27th
Annual Int'l Symposium on Microarchitecture 1994;63-74.
476. Rau BR, Glaeser CD, Picard RL. Efficient code generation for horizontal architectures: Com-
piler techniques and architectural support. Proc Ninth Annual Int'l Symposium on Computer
Architecture (ISCA) 1982;131-139.
477. Rau BR, Yen DWL, Yen W, Towle RA. The Cydra 5 departmental supercomputer: Design
philosophies, decisions, and trade-offs. IEEE Computers . 1989;22(1):12-34 (January).
478. Reddi VJ, Lee BC, Chilimbi T, Vaid K. Web search using mobile cores: Quantifying and
mitigating the price of efficiency. Proc 37th Annual Int'l Symposium on Computer Architecture
(ISCA) 2010.
479. Redmond KC, Smith TM. Project Whirlwind—The History of a Pioneer Computer Boston:
Digital Press; 1980.
480. Reinhardt SK, Larus JR, Wood DA. Tempest and Typhoon: User-level shared memory. 21st
Annual Int'l Symposium on Computer Architecture (ISCA) 1994;325-336.
481. Reinman G, Jouppi NP. Extensions to CACTI. In: research.compaq.com/wrl/people/jouppi/
CACTI.html ; 1999.
482. Retberg RD, Crowther WR, Carvey PP, Towlinson RS. The Monarch parallel processor
hardware design. IEEE Computer . 1990;23(4):18-30 (April).
483. Riemens A, Vissers KA, Schuten RJ, Sijstermans FW, Hekstra GJ, La Hei GD. Trimedia
CPU64 application domain and benchmark suite. Proc IEEE Int'l Conf on Computer Design:
VLSI in Computers and Processors (ICCD'99) 1999;580-585.
484. Riseman EM, Foster CC. Percolation of code to enhance paralled dispatching and execu-
tion. IEEE Trans on Computers . 1972;C-21(12):1411-1415 (December).
485. Robin J, Irvine C. Analysis of the Intel Pentium's ability to support a secure virtual machine
monitor. Proc USENIX Security Symposium 2000.
486. Robinson B, Blount L. The VM/HPO 3880-23 Performance Results Gaithersburg, Md: IBM
Tech. Bulletin GG66-0247-00, IBM Washington Systems Center; 1986.
487. Ropers, A., H. W Lollman, J. Wellhausen [1999]. DSPstone: Texas Instruments
TMS320C54x, Tech. Rep. IB 315 1999/9-ISS-Version 0.9, Aachen University of Technology,
Aaachen, Germany ( www.ert.rwth-aachen.de/Projekte/Tools/coal/dspstone_c54x/index.html ).
488. Rosenblum M, Herrod SA, Witchel E, Gupta A. Complete computer simulation: The
SimOS approach. in IEEE Parallel and Distributed Technology (now called Concurrency) .
1995;4(3):34-43.
489. Rowen C, Johnson M, Ries P. The MIPS R3010 floating-point coprocessor. IEEE Micro .
1988;8(3):53-62 (June).