Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 671

maximum steady-state number of write ports needed is 1. Instead, we choose to detect and
enforce access to the write port as a structural hazard.
FIGURE C.38 Three instructions want to perform a write-back to the FP register file
simultaneously, as shown in clock cycle 11 . This is not the worst case, since an earlier di-
vide in the FP unit could also finish on the same clock. Note that although the MUL.D , ADD.D , and
L.D all are in the MEM stage in clock cycle 10, only the L.D actually uses the memory, so no
structural hazard exists for MEM.
There are two different ways to implement this interlock. The first is to track the use of the
write port in the ID stage and to stall an instruction before it issues, just as we would for any
other structural hazard. Tracking the use of the write port can be done with a shift register
that indicates when already-issued instructions will use the register file. If the instruction in
ID needs to use the register file at the same time as an instruction already issued, the instruc-
tion in ID is stalled for a cycle. On each clock the reservation register is shifted 1 bit. This im-
plementation has an advantage: It maintains the property that all interlock detection and stall
insertion occurs in the ID stage. The cost is the addition of the shift register and write conflict
logic. We will assume this scheme throughout this section.
An alternative scheme is to stall a conflicting instruction when it tries to enter either the
MEM or WB stage. If we wait to stall the conflicting instructions until they want to enter the
MEM or WB stage, we can choose to stall either instruction. A simple, though sometimes sub-
optimal, heuristic is to give priority to the unit with the longest latency, since that is the one
most likely to have caused another instruction to be stalled for a RAW hazard. The advantage
of this scheme is that it does not require us to detect the conflict until the entrance of the MEM
or WB stage, where it is easy to see. The disadvantage is that it complicates pipeline control,
as stalls can now arise from two places. Notice that stalling before entering MEM will cause
the EX, A4, or M7 stage to be occupied, possibly forcing the stall to trickle back in the pipeline.
Likewise, stalling before WB would cause MEM to back up.
Our other problem is the possibility of WAW hazards. To see that these exist, consider the
example in Figure C.38 . If the L.D instruction were issued one cycle earlier and had a destin-
ation of F2, then it would create a WAW hazard, because it would write F2 one cycle earlier
than the ADD.D . Note that this hazard only occurs when the result of the ADD.D is overwritten
without any instruction ever using it! If there were a use of F2 between the ADD.D and the L.D ,
the pipeline would need to be stalled for a RAW hazard, and the L.D would not issue until the
ADD.D was completed. We could argue that, for our pipeline, WAW hazards only occur when a