Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 672

useless instruction is executed, but we must still detect them and make sure that the result of
the L.D appears in F2 when we are done. (As we will see in Section C.8 , such sequences some-
times do occur in reasonable code.)
There are two possible ways to handle this WAW hazard. The first approach is to delay the
issue of the load instruction until the ADD.D enters MEM. The second approach is to stamp out
the result of the ADD.D by detecting the hazard and changing the control so that the ADD.D does
not write its result. Then the L.D can issue right away. Because this hazard is rare, either scheme
will work fine—you can pick whatever is simpler to implement. In either case, the hazard can
be detected during ID when the L.D is issuing, and stalling the L.D or making the ADD.D a no-op
is easy. The difficult situation is to detect that the L.D might finish before the ADD.D , because that
requires knowing the length of the pipeline and the current position of the ADD.D . Luckily, this
code sequence (two writes with no intervening read) will be very rare, so we can use a simple
solution: If an instruction in ID wants to write the same register as an instruction already is-
sued, do not issue the instruction to EX. In Section C.7 , we will see how additional hardware
can eliminate stalls for such hazards. First, let's put together the pieces for implementing the
hazard and issue logic in our FP pipeline.
In detecting the possible hazards, we must consider hazards among FP instructions, as well
as hazards between an FP instruction and an integer instruction. Except for FP loads-stores
and FP-integer register moves, the FP and integer registers are distinct. All integer instruc-
tions operate on the integer registers, while the FP operations operate only on their own re-
gisters. Thus, we need only consider FP loads-stores and FP register moves in detecting hazar-
ds between FP and integer instructions. This simplification of pipeline control is an additional
advantage of having separate register files for integer and floating-point data. (The main ad-
vantages are a doubling of the number of registers, without making either set larger, and an
increase in bandwidth without adding more ports to either set. The main disadvantage, bey-
ond the need for an extra register file, is the small cost of occasional moves needed between
the two register sets.) Assuming that the pipeline does all hazard detection in ID, there are
three checks that must be performed before an instruction can issue:
1. Check for structural hazards —Wait until the required functional unit is not busy (this is only
needed for divides in this pipeline) and make sure the register write port is available when
it will be needed.
2. Check for a RAW data hazard —Wait until the source registers are not listed as pending des-
tinations in a pipeline register that will not be available when this instruction needs the
result. A number of checks must be made here, depending on both the source instruction,
which determines when the result will be available, and the destination instruction, which
determines when the value is needed. For example, if the instruction in ID is an FP opera-
tion with source register F2, then F2 cannot be listed as a destination in ID/A1, A1/A2, or
A2/A3, which correspond to FP add instructions that will not be finished when the instruc-
tion in ID needs a result. (ID/A1 is the portion of the output register of ID that is sent to
A1.) Divide is somewhat more tricky, if we want to allow the last few cycles of a divide to
be overlapped, since we need to handle the case when a divide is close to finishing as spe-
cial. In practice, designers might ignore this optimization in favor of a simpler issue test.
3. Check for a WAW data hazard —Determine if any instruction in A1, …, A4, D, M1, …, M7 has
the same register destination as this instruction. If so, stall the issue of the instruction in ID.
Although the hazard detection is more complex with the multicycle FP operations, the con-
cepts are the same as for the MIPS integer pipeline. The same is true for the forwarding logic.
The forwarding can be implemented by checking if the destination register in any of the EX/
MEM, A4/MEM, M7/MEM, D/MEM, or MEM/WB registers is one of the source registers of a