Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 656

C.27 shows the relevant segments of the pipelined data path with the additional multiplexers
and connections in place.
FIGURE C.27 Forwarding of results to the ALU requires the addition of three extra in-
puts on each ALU multiplexer and the addition of three paths to the new inputs . The
paths correspond to a bypass of: (1) the ALU output at the end of the EX, (2) the ALU output
at the end of the MEM stage, and (3) the memory output at the end of the MEM stage.
For MIPS, the hazard detection and forwarding hardware is reasonably simple; we will see
that things become somewhat more complicated when we extend this pipeline to deal with
loating point. Before we do that, we need to handle branches.
Dealing With Branches In The Pipeline
In MIPS, the branches ( BEQ and BNE ) require testing a register for equality to another register,
which may be R0 . If we consider only the cases of BEQZ and BNEZ , which require a zero test, it
is possible to complete this decision by the end of the ID cycle by moving the zero test into
that cycle. To take advantage of an early decision on whether the branch is taken, both PCs
(taken and untaken) must be computed early. Computing the branch-target address during
ID requires an additional adder because the main ALU, which has been used for this func-
tion so far, is not usable until EX. Figure C.28 shows the revised pipelined data path. With the
separate adder and a branch decision made during ID, there is only a 1-clock-cycle stall on
branches. Although this reduces the branch delay to 1 cycle, it means that an ALU instruction
followed by a branch on the result of the instruction will incur a data hazard stall. Figure C.29
shows the branch portion of the revised pipeline table from Figure C.23 .