Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 655

FIGURE C.26 Forwarding of data to the two ALU inputs (for the instruction in EX) can
occur from the ALU result (in EX/MEM or in MEM/WB) or from the load result in MEM/
WB . There are 10 separate comparisons needed to tell whether a forwarding operation should
occur. The top and bottom ALU inputs refer to the inputs corresponding to the first and second
ALU source operands, respectively, and are shown explicitly in Figure C.21 on page C-34 and
in Figure C.27 on page C-41. Remember that the pipeline latch for destination instruction in
EX is ID/EX, while the source values come from the ALUOutput portion of EX/MEM or MEM/
WB or the LMD portion of MEM/WB. There is one complication not addressed by this logic:
dealing with multiple instructions that write the same register. For example, during the code
sequence DADD R1, R2, R3; DADDI R1, R1, #2; DSUB R4, R3, R1 , the logic must ensure that the DSUB
instruction uses the result of the DADDI instruction rather than the result of the DADD instruction.
The logic shown above can be extended to handle this case by simply testing that forwarding
from MEM/WB is enabled only when forwarding from EX/MEM is not enabled for the same in-
put. Because the DADDI result will be in EX/MEM, it will be forwarded, rather than the DADD result
in MEM/WB.
In addition to the comparators and combinational logic that we must determine when a for-
warding path needs to be enabled, we also must enlarge the multiplexers at the ALU inputs
and add the connections from the pipeline registers that are used to forward the results. Figure