Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 653

FIGURE C.24 Situations that the pipeline hazard detection hardware can see by com-
paring the destination and sources of adjacent instructions . This table indicates that the
only comparison needed is between the destination and the sources on the two instructions
following the instruction that wrote the destination. In the case of a stall, the pipeline depend-
ences will look like the third case once execution continues. Of course, hazards that involve
R0 can be ignored since the register always contains 0, and the test above could be extended
to do this.
Let's start with implementing the load interlock. If there is a RAW hazard with the source
instruction being a load, the load instruction will be in the EX stage when an instruction that
needs the load data will be in the ID stage. Thus, we can describe all the possible hazard situ-
ations with a small table, which can be directly translated to an implementation. Figure C.25
shows a table that detects all load interlocks when the instruction using the load result is in
the ID stage.