Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 654

FIGURE C.25 The logic to detect the need for load interlocks during the ID stage of an
instruction requires three comparisons . Lines 1 and 2 of the table test whether the load
destination register is one of the source registers for a register-register operation in ID. Line 3
of the table determines if the load destination register is a source for a load or store effective
address, an ALU immediate, or a branch test. Remember that the IF/ID register holds the
state of the instruction in ID, which potentially uses the load result, while ID/EX holds the state
of the instruction in EX, which is the load instruction.
Once a hazard has been detected, the control unit must insert the pipeline stall and prevent
the instructions in the IF and ID stages from advancing. As we said earlier, all the control in-
formation is carried in the pipeline registers. (Carrying the instruction along is enough, since
all control is derived from it.) Thus, when we detect a hazard we need only change the control
portion of the ID/EX pipeline register to all 0s, which happens to be a no-op (an instruction
that does nothing, such as DADD R0,R0,R0 ). In addition, we simply recirculate the contents of the
IF/ID registers to hold the stalled instruction. In a pipeline with more complex hazards, the
same ideas would apply: We can detect the hazard by comparing some set of pipeline registers
and shift in no-ops to prevent erroneous execution.
Implementing the forwarding logic is similar, although there are more cases to consider. The
key observation needed to implement the forwarding logic is that the pipeline registers con-
tain both the data to be forwarded as well as the source and destination register fields. All for-
warding logically happens from the ALU or data memory output to the ALU input, the data
memory input, or the zero detection unit. Thus, we can implement the forwarding by a com-
parison of the destination registers of the IR contained in the EX/MEM and MEM/WB stages
against the source registers of the IR contained in the ID/EX and EX/MEM registers. Figure
C.26 shows the comparisons and possible forwarding operations where the destination of the
forwarded result is an ALU input for the instruction currently in EX.