Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 652

To control this simple pipeline we need only determine how to set the control for the four
multiplexers in the data path of Figure C.22 . The two multiplexers in the ALU stage are set
depending on the instruction type, which is dictated by the IR field of the ID/EX register. The
top ALU input multiplexer is set by whether the instruction is a branch or not, and the bot-
tom multiplexer is set by whether the instruction is a register-register ALU operation or any
other type of operation. The multiplexer in the IF stage chooses whether to use the value of
the incremented PC or the value of the EX/MEM.ALUOutput (the branch target) to write in-
to the PC. This multiplexer is controlled by the field EX/MEM.cond. The fourth multiplexer is
controlled by whether the instruction in the WB stage is a load or an ALU operation. In addi-
tion to these four multiplexers, there is one additional multiplexer needed that is not drawn in
Figure C.22 , but whose existence is clear from looking at the WB stage of an ALU operation.
The destination register field is in one of two different places depending on the instruction
type (register-register ALU versus either ALU immediate or load). Thus, we will need a mul-
tiplexer to choose the correct portion of the IR in the MEM/WB register to specify the register
destination field, assuming the instruction writes a register.
Implementing The Control For The MIPS Pipeline
The process of leting an instruction move from the instruction decode stage (ID) into the ex-
ecution stage (EX) of this pipeline is usually called instruction issue; an instruction that has
made this step is said to have issued . For the MIPS integer pipeline, all the data hazards can be
checked during the ID phase of the pipeline. If a data hazard exists, the instruction is stalled
before it is issued. Likewise, we can determine what forwarding will be needed during ID and
set the appropriate controls then. Detecting interlocks early in the pipeline reduces the hard-
ware complexity because the hardware never has to suspend an instruction that has updated
the state of the processor, unless the entire processor is stalled. Alternatively, we can detect
the hazard or forwarding at the beginning of a clock cycle that uses an operand (EX and MEM
for this pipeline). To show the differences in these two approaches, we will show how the in-
terlock for a read after write (RAW) hazard with the source coming from a load instruction
(called a load interlock ) can be implemented by a check in ID, while the implementation of for-
warding paths to the ALU inputs can be done during EX. Figure C.24 lists the variety of cir-
cumstances that we must handle.