Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 651

the first two stages are independent of the current instruction type; they must be independent
because the instruction is not decoded until the end of the ID stage. The IF activity depends on
whether the instruction in EX/MEM is a taken branch. If so, then the branch-target address of
the branch instruction in EX/MEM is writen into the PC at the end of IF; otherwise, the incre-
mented PC will be writen back. (As we said earlier, this effect of branches leads to complic-
ations in the pipeline that we deal with in the next few sections.) The fixed-position encoding
of the register source operands is critical to allowing the registers to be fetched during ID.
FIGURE C.23 Events on every pipe stage of the MIPS pipeline . Let's review the actions in
the stages that are specific to the pipeline organization. In IF, in addition to fetching the in-
struction and computing the new PC, we store the incremented PC both into the PC and into a
pipeline register (NPC) for later use in computing the branch-target address. This structure is
the same as the organization in Figure C.22 , where the PC is updated in IF from one of two
sources. In ID, we fetch the registers, extend the sign of the lower 16 bits of the IR (the imme-
diate field), and pass along the IR and NPC. During EX, we perform an ALU operation or an
address calculation; we pass along the IR and the B register (if the instruction is a store). We
also set the value of cond to 1 if the instruction is a taken branch. During the MEM phase, we
cycle the memory, write the PC if needed, and pass along values needed in the final pipe
stage. Finally, during WB, we update the register field from either the ALU output or the
loaded value. For simplicity we always pass the entire IR from one stage to the next, although
as an instruction proceeds down the pipeline, less and less of the IR is needed.