Pipelining: Basic and Intermediate Concepts - Computer Architecture: A Quantitative Approach - page 650

FIGURE C.22 The data path is pipelined by adding a set of registers, one between each
pair of pipe stages . The registers serve to convey values and control information from one
stage to the next. We can also think of the PC as a pipeline register, which sits before the IF
stage of the pipeline, leading to one pipeline register for each pipe stage. Recall that the PC is
an edge-triggered register written at the end of the clock cycle; hence, there is no race condi-
tion in writing the PC. The selection multiplexer for the PC has been moved so that the PC is
written in exactly one stage (IF). If we didn't move it, there would be a conflict when a branch
occurred, since two instructions would try to write different values into the PC. Most of the
data paths flow from left to right, which is from earlier in time to later. The paths flowing from
right to left (which carry the register write-back information and PC information on a branch)
introduce complications into our pipeline.
All of the registers needed to hold values temporarily between clock cycles within one in-
struction are subsumed into these pipeline registers. The fields of the instruction register (IR),
which is part of the IF/ID register, are labeled when they are used to supply register names.
The pipeline registers carry both data and control from one pipeline stage to the next. Any
value needed on a later pipeline stage must be placed in such a register and copied from one
pipeline register to the next, until it is no longer needed. If we tried to just use the temporarily
registers we had in our earlier unpipelined data path, values could be overwritten before all
uses were completed. For example, the field of a register operand used for a write on a load
or ALU operation is supplied from the MEM/WB pipeline register rather than from the IF/ID
register. This is because we want a load or ALU operation to write the register designated by
that operation, not the register field of the instruction currently transitioning from IF to ID!
This destination register field is simply copied from one pipeline register to the next, until it is
needed during the WB stage.
Any instruction is active in exactly one stage of the pipeline at a time; therefore, any actions
taken on behalf of an instruction occur between a pair of pipeline registers. Thus, we can also
look at the activities of the pipeline by examining what has to happen on any pipeline stage
depending on the instruction type. Figure C.23 shows this view. Fields of the pipeline registers
are named so as to show the flow of data from one stage to the next. Notice that the actions in